350px-SPI_single_slave.svg.png
SPI bus: single master and single slave


400px-SPI_8-bit_circular_transfer.svg.png
A typical hardware setup using two shift registers to form an inter-chip circular buffer


400px-SPI_timing_diagram2.svg.png
A timing diagram showing clock polarity and phase


ModeCPOLCPHA
000
101
210
311



350px-SPI_three_slaves.svg.png
Typical SPI bus: master and three independent slaves


350px-SPI_three_slaves_daisy_chained.svg.png
Daisy-chained SPI bus: master and cooperative slaves


unsigned char SPIBitBang8BitsMode0(unsigned char byte)
{       
    unsigned char bit;
 
    for (bit = 0; bit < 8; bit++) {
        /* write MOSI on trailing edge of previous clock */
        if (byte & 0x80)
            SETMOSI();
        else
            CLRMOSI();
        byte <<= 1;
 
        /* half a clock cycle before leading/rising edge */
        SPIDELAY(SPISPEED/2);
        SETCLK();
 
        /* half a clock cycle before trailing/falling edge */
        SPIDELAY(SPISPEED/2);
 
        /* read MISO on trailing edge */
        byte |= READMISO();
        CLRCLK();
    }
 
    return byte;
}

Advantages

  • Full duplex communication
  • Higher throughput than I²C or SMBus
  • Complete protocol flexibility for the bits transferred
    • Not limited to 8-bit words
    • Arbitrary choice of message size, content, and purpose
  • Extremely simple hardware interfacing
    • Typically lower power requirements than I²C or SMBus due to less circuitry (including pullups)
    • No arbitration or associated failure modes
    • Slaves use the master's clock, and don't need precision oscillators
    • Slaves don't need a unique address -- unlike I²C or GPIB or SCSI
    • Transceivers are not needed
  • Uses only four pins on IC packages, and wires in board layouts or connectors, much less than parallel interfaces
  • At most one "unique" bus signal per device (chip select); all others are shared
  • Signals are unidirectional allowing for easy Galvanic isolation


Disadvantages

  • Requires more pins on IC packages than I²C, even in the "3-Wire" variant
  • No in-band addressing; out-of-band chip select signals are required on shared buses
  • No hardware flow control by the slave (but the master can delay the next clock edge to slow the transfer rate)
  • No hardware slave acknowledgment (the master could be "talking" to nothing and not know it)
  • Supports only one master device
  • No error-checking protocol is defined
  • Generally prone to noise spikes causing faulty communication
  • Without a formal standard, validating conformance is not possible
  • Only handles short distances compared to RS-232RS-485, or CAN-bus

Applications

The board real estate savings compared to a parallel I/O bus are significant, and have earned SPI a solid role in embedded systems. That is true for most system-on-a-chip processors, both with higher end 32-bit processors such as those using ARMMIPS, or PowerPC and with other microcontrollers such as the AVRPIC, and MSP430. These chips usually include SPI controllers capable of running in either master or slave mode. In-system programmable AVR controllers (including blank ones) can be programmed using an SPI interface.[3]

Chip or FPGA based designs sometimes use SPI to communicate between internal components; on-chip real estate can be as costly as its on-board cousin.

The full-duplex capability makes SPI very simple and efficient for single master/single slave applications. Some devices use the full-duplex mode to implement an efficient, swift data stream for applications such as digital audiodigital signal processing, or telecommunications channels, but most off-the-shelf chips stick to half-duplex request/response protocols.

SPI is used to talk to a variety of peripherals, such as

  • Sensors: temperature, pressure, ADC, touchscreens, video game controllers
  • Control devices: audio codecs, digital potentiometers, DAC
  • Camera lenses: Canon EF lens mount
  • Communications: Ethernet, USB, USART, CAN, IEEE 802.15.4IEEE 802.11, handheld video games
  • Memory: flash and EEPROM
  • Real-time clocks
  • LCD displays, sometimes even for managing image data
  • Any MMC or SD card (including SDIO variant)

For high performance systems, FPGAs sometimes use SPI to interface as a slave to a host, as a master to sensors, or for flash memory used to bootstrap if they are SRAM-based.

JTAG is essentially an application stack for a 3-wire SPI flavor, using different signal names[citation needed]: TCK not SCK, TDI not MOSI, TDO not MISO. It defines a state machine (driven by a TMS signal instead of a chip select line), protocol messages, a core command set, the ability to daisy-chain devices in a "scan chain", and how vendors define new commands. The devices in a scan chain are initially treated as a single device, and transitions on TMS update their state machines; once the individual devices are identified, commands may be issued that affect only one device in that scan chain. Different vendors use different JTAG connectors. Bit strings used in JTAG are often long and not multiples of 8 bit words; for example, a boundary scan reports signal state on each of several hundred pins.

SGPIO is essentially another (incompatible) application stack for SPI designed for particular backplane management activities[citation needed]. SGPIO uses 3-bit messages.


Standards

The SPI bus is a de facto standard. However, the lack of a formal standard is reflected in a wide variety of protocol options. Different word sizes are common. Every device defines its own protocol, including whether or not it supports commands at all. Some devices are transmit-only; others are receive-only. Chip selects are sometimes active-high rather than active-low. Some protocols send the least significant bit first.

Some devices even have minor variances from the CPOL/CPHA modes described above. Sending data from slave to master may use the opposite clock edge as master to slave. Devices often require extra clock idle time before the first clock or after the last one, or between a command and its response. Some devices have two clocks, one to "capture" or "display" data, and another to clock it into the device. Many of these "capture clocks" run from the chip select line.

Some devices require an additional flow control signal from slave to master, indicating when data are ready. This leads to a "five wire" protocol instead of the usual four. Such a "ready" or "enable" signal is often active-low, and needs to be enabled at key points such as after commands or between words. Without such a signal, data transfer rates may need to be slowed down significantly, or protocols may need to have "dummy bytes" inserted, to accommodate the worst case for the slave response time. Examples include initiating an ADC conversion, addressing the right page of flash memory, and processing enough of a command that device firmware can load the first word of the response. (Many SPI masters don't support that signal directly, and instead rely on fixed delays.)

Many SPI chips only support messages that are multiples of 8 bits. Such chips can not interoperate with the JTAG or SGPIO protocols, or any other protocol that requires messages that are not multiples of 8 bits.

There are even hardware-level differences. Some chips combine MOSI and MISO into a single data line (SI/SO); this is sometimes called "3-Wire" signaling (in contrast to normal "4-wire" SPI). Another SPI flavor removes the chip select line, managing protocol state machine entry/exit using other methods; this isn't usually called 3-Wire though. Anyone needing an external connector for SPI defines their own -- UEXTJTAG connectorSecure Digital card socket, etc. . Signal levels depend entirely on the chips involved.



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